Control system for chained circuit modules

ABSTRACT

A wafer-scale integrated circuit comprises a few hundred modules which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs XINN, XINE, XINS, XINW from neighbouring modules and outputs thereto XOUTN, XOUTE, XOUTS, XOUTW, only one of which is enabled to by one of four selection signals SELN, SELE, SELS, SELW acting both on transmit path logic and on receive path logic in a return path. A RAM unit can be enabled by WRITE to write a block of data sent to RID via the transmit path and can be enabled by READ to read a block of data to ROD for return along the return path. The provision of SELN, etc. READ and WRITE is effected by configuration logic which includes a shift register and is responsive to a command mode signal CMND, on a line which runs to all modules in parallel. If, when CMND is asserted the bit currently in the transmit path is logic (, the module is not addressed. IF the bit is 1, the modules is addressed and the bit is latched as a token within the XMIT path logic. The configuration logic then clocks the 1 bit token along its shift register until CMND goes low again. The first six stages of the shift register provide SELN, SELE, SELS, SELW, READ and WRITE respectively and the position of the token when CMND goes low determines which command is generated. The shift register has further stages for providing a signal ACR to reset an address counter in the RAM unit and for toggling RPON which controls the power supply to the RAM unit via a transistor switch.

The present invention relates to a control system for chained circuitmodules. It is known to connect a plurality of circuit modules in achain, each module being capable of performing some memory and/or dataprocessing operation. In particular, the circuit modules may be undicedchip areas of an integrated circuit wafer and the chain of modules maybe grown by actuation of electronic switching functions within themodules, as described in GB 1 377 859. The chain may be single (andapproximate a spiral) or may be branched.

As described in GB 1 377 859 it is necessary to be able to send commandsto the circuit modules individually. The commands are used incontrolling the growth of the chain and also in controlling operationscarried out using the circuit modules. For example, it may be necessaryto command the writing of data to or the reading of data from a memorymodule. A module may be regarded as composed of a function unit, whichperforms the memory or data processing operation proper of the unit, andcontrol logic which responds to commands. Various techniques have beensuggested for addressing commands to individual modules. Each module maybe given its own address and commands can include address fields,whereby associative addressing is employed. This provides completelyflexible addressing (any command can be sent to any module in the chain)but suffers from the disadvantages that every module has to be set upwith its own address and the control logic is relatively complex. Animproved proposal (see again GB 1 377 859) utilises an address number ineach command. As the command passes from module to module, the addressnumber is decremented or incremented until a predetermined number isreached (e.g. zero), whereupon the command is executed by the module atwhich this event occurs. This avoids the need to set up modules withindividual addresses but the control logic is still relatively complex.

Another idea proposed in GB 1 377 859 is to issue a global command toall modules. Such a command is issued by way of a global line, that isto say a line running to all modules in parallel, in contrast to lineschained through the modules. Other global lines can include power andclock lines. A module performs a specific function when it receives theglobal command and the module is concurrently receiving a specific statesignal from an adjacent module. In GB 1 377 859 this is proposed as partof the mechanism for growing the chain of modules. It is of extremelylimited application, enabling one particular command to be sent only tothe end of the chain. In use of the chain of modules, it is obviouslynecessary to be able to address various commands to modules anywherealong the chain.

An important consideration in the case of chained modules is theintegrity of the chaining paths between modules. These include part ofthe control logic of each module and this part will be called the seriallogic. The control logic will additionally include side-chain logic,that is to say logic which is branched off the path through which themodules are chained. Any defect in the serial logic of a module willbreak the chain and render the apparatus inoperable. Particularly whenthe modules are undiced chip areas, i.e. parts of a wafer scaleintegration (WSI) system, there is a high premium on keeping the seriallogic as simple as possible. As is well known, a significant problem inWSI is avoidance of faulty modules. It is advantageous to be able toutilise the serial logic of a faulty module (provided the serial logicis functioning) even although the function unit of the module is notused, and may even be disabled, because it is faulty. The use of goodserial logic of otherwise faulty modules makes it possible to growchains more efficiently and include within the chain a higher proportionof non-faulty modules than if the chain excludes a module which is inany way faulty, (which is the approach adopted in GB 1 377 859).

The object of the present invention is to provide a control system whichenables flexible addressing to be achieved using relatively simplecontrol logic.

A more specific object of the preferred implementation of the inventionis to enable flexible addressing to be achieved with extremely simpleserial logic.

According to the invention in its broadest aspect there is provided acontrol system for chained circuit modules, each of which can execute aselected one of a repertoire of commands, wherein each module includes ashift register arrangement responsive to clock pulses provided to allmodules in the chain, all modules are connected to a global commandline, and each module is operative to execute a selected command onreceipt of a command signal on the global command line when a token isthen present in its shift register arrangement, the command selectionbeing at least partially determined by the position of the token withinthe shift register arrangement.

The token could consist of more than one bit and the selection of acommand could then be determined in part by the location of the tokenand in part by a decode of the token itself. However, it is preferred touse a single bit token (such as a "1" in a stream of zeroes) and to makecommand selection dependent solely upon the location of the token whenthe global command signal is received. Further description will proceedin accordance with use of a single bit token, i.e. a token bit.

A straightforward but non-preferred implementation of the invention willfirstly be described. If the repertoire of commands comprises commands 1... j... m where m may be 8 for example, each module can include anm-bit shift register in its serial logic. To cause the i^(th) module toimplement the j^(th) commands, a token bit is launched down the chain ofmodules and, after (i×m)+j clock pulses the token bit will be in thej^(th) command bit of the i^(th) module. The global command is thenissued to all modules. Because of the location of the token bit, thei^(th) module executes the j^(th) command.

The above implementation suffers from two drawbacks. The serial logic ismore extensive than is desirable (compare the above comments) and thelatency for command execution is high. There may be some hundreds ofmodules in the chain and, if i=100 and m=8, it takes 792 clock pulses toget a token bit to the i^(th) module.

In accordance with an important development of the invention, the shiftregister arrangement is mainly or wholly in the side-chain logic. Theserial logic includes very few, preferably only one, bit buffer stages.Two global command signals are now required. The first causes a token tobe seized at a module and to be clocked down its side-chain shiftregister arrangement. The second causes the module in question toexecute a command in dependence upon its position which the token hasreached along the side-chain shift register arrangement. The first andsecond global command signals could be provided by way of separateglobal lines but it is much preferred to use a single global line and toprovide both signals on this line. Again the preferred technique is torepresent one signal by asserting a particular logic level and torepresent the second signal by terminating this assertion. In theembodiment to be described below the first signal is given when CMNDgoes true, the second when CMND reverts to false.

When a token is seized at a module it may be arrested in that moduleuntil the second signal, when it may be allowed to proceed to moreremote modules; this is the option selected in the embodiment describedbelow. Alternatively the token may be seized "on the fly" and be allowedto continue on its way for use on a subsequent assertion of the firstsignal.

Assuming there to be only a single bit buffer in the serial logic ofeach module, the latency in executing the j^(th) command at the i^(th)module is only i+j clock pulses.

The invention will be described in more detail, by way of example, withreference to the accompanying drawings:

FIG. 1 shows part of a WSI circuit including global lines,

FIG. 2 shows part of a WSI circuit but shows the transmit pathinter-module lines,

FIG. 3 is similar to FIG. 2 but shows the receive path intermodulelines,

FIG. 4 illustrates how a chain of modules is formed at the edge of awafer,

FIG. 5 is a general block diagram of a module,

FIG. 6 is a block diagram of a memory unit forming the function unit ofa module,

FIGS. 7 and 8 are circuit diagrams of transmit and receive path logicrespectively,

FIGS. 9 and 10 are circuit diagrams of two portions of the configurationlogic of a module,

FIG. 11 is a block diagram of a circuit for sending commands to modules,and

FIG. 12 shows explantory waveforms pertaining to FIG. 11.

FIG. 1 shows a few modules 10 on a wafer which may contain a few hundredmodules arranged on the wafer. The modules are set in a grid of globallines, namely a V_(DD) power line 11, a V_(SS) power line 12, a WCK(wafer clock) line 13 and a CMND (command) line 14. All these lines goto bondsites on the edge of the wafer or WCK and CMND may go to acommand module on the wafer.

FIG. 2 shows the same modules 10 minus the global lines but withinter-module lines 15 for transmit paths. Data may be sent through achain of modules, starting at a bondsite identified as XMIT (transmit;not shown). The modules have four connections into their XMIT path andthese connections are identified as follows:

XINN from module above

XINE from module to right

XINS from module below

XINW from module to left

As shown in the right hand module only, these XIN lines merge into asingle XIN terminal.

The modules have four connections out from their XMIT paths and . theseconnections are identified as follows:

XOUTN to module above

XOUTE to module to right

XOUTS to module below

XOUTW to module to left.

Unlike the XIN lines, these output lines are switched so that a modulecan select only one of its edge neighbours as the next module in thechain, on to which XMIT data is passed.

The modules are also connected by receive path inter-module lines 16(FIG. 3) which allow data to be sent back to a bondsite identified asRECV (not shown).

The modules have four connections into their RECV paths:

RINN from module above

RINE from module to right

RINS from module below

RINW from module to left.

These connections are switched in correspondence with XOUT connections.

The modules have four connections out of their RECV paths:

ROUTN to module above

ROUTE to module to right

ROUTS to module below

ROUTW to module to left.

These connections branch, without switching, from an OUT terminal, sothat return data is broadcast to all four neighbours, only one of whichwill have been set up to receive it.

The XOUT and RIN selections are effected by four selection signals SELN,SELE, SELS and SELW, whose generation is explained below. Only one ofthese signals can be true. If SELN is true, for example, the moduleroutes the XMIT path to the adjacent module above and accepts RECV datafrom that module.

The SEL signals of the modules are set up basically as described in GB 1377 859. Modules are added one by one to the chain, tested and retainedif good, and the procedure is reiterated to grow a chain ofinterconnected modules. The chain tends to spiral in to the centre ofthe wafer in the case of a peripheral bondsite for XMIT and RECV. Theremay be a plurality of such bondsites, say four, to improve the chance offinding a good place to start the chain. The testing is effected instages in the present system, as described further below.

FIG. 4 illustrates a peripheral fragment 17 of a wafer with modules 10and the bondsite terminals XMIT and RECV. Portions of the XMIT path andRECV path are shown in full and broken lines respectively, as they wouldbe grown through modules in accordance with the algorithm that eachmodule tries its selection options in the order SELN, SELE, SELS andSELW. The first module M1 fails with SELN (there is no module above it)but succeeds with SELE, so adding M2 to the chain. M2 succeeds with SELNand adds M3. M3 fails with SELN but succeeds with SELE, to add M4. M5succeeds with SELN to add M5, and so on. In the example shown allmodules are good, at least so far as their control logic is concerned.

Before turning to a full description of a module 10, a brief summary ofthe way in which it operates will be given. Normally the module merelyacts as a link in the chain and outbound data and commands pass fromXMIT through the XMIT path in the module with a 1-bit delay through eachmodule. Inbound data returns to RECV through the RECV path in themodule, also with a 1-bit delay through each module. Each module,contains a 16 k×1 bit dynamic RAM unit which is constantly refreshedunder control of a free-running address counter. The module alsocontains control logic which can respond to commands to effect SELN,SELE, SELLS and SELW and to other commands of which the most importantare READ and WRITE. When a module receives either of these commands, thechain is broken at that module and the RAM unit is written to in thecase of WRITE and read from in the case of READ. Although the RAM unitis composed of random access blocks it is only addressed by the freerunning counter and treated as a 16k block of serial memory. In a READoperation, all 16k of memory are read out on to the RECV line. If theread command is timed correctly in relation to the address countercycle, the memory block will be read out correctly starting from addressO and running through to address (2¹⁶⁻⁻ -l). If the READ command is notthus timed, the data will be "wrapped round"--in an address order N, . .. , (2¹⁶ --i), O, . . . , (N-1) where N is the address obtaining at theREAD command. The data can be accepted in this order to RECV and thencyclically shifted to establish the correct address order.

In a WRITE operation 16k of data is written from XMIT into the RAM unit.The command and ensuring data can either be correctly timed in relationto the address counter cycle or can be pre-wrapped-round to match theaddress N at which the write starts. Another possibility is to writeregardless and store the value in the address counter cycle marking thestart of the written block, this stored value being used when the blockis read to enable it to be correctly unwrapped.

After a read or a write operation, assuming that communication is thenrequired to the more remote modules, it is necessary to send theappropriate SEL command to the module to re-establish the chain and itis accordingly necessary to maintain a record of the SEL commandrequired by each module. Thus a table is established during initialtesting and preferably then frozen in a PROM. This table identifies themodules simply by their number along the chain and provides informationof the following kind,.to take the example of FIG. 4:

    ______________________________________                                        ENTRY       SEL       OFFSET      FLAG                                        ______________________________________                                        M1          E                                                                 M2          N                                                                 M3          E                                                                 M4          N                                                                 M5          E                                                                 ______________________________________                                    

ENTRY is the table address. SEL requires two bits (e.g. 00 =SELN,01=SELE 10=SELS and 11 SELW) OFFSET gives the number in the module'saddress counter at a datum address cycle time, corrected to take accountof the time taken to access the module (1-bit delay through eachpreceding module). FLAG is a single bit which indicates whether the RAMunit of the module is usable.

It is not essential to know OFFSET. If a data block includes a suitableframing word 16k blocks may be written and read without regard towrap-round. After reading a block it may be "unwrapped" by finding theframing word.

A more detailed description of a module will now be give with anexplanation as to how the aforementioned facilities are provided andother features of the preferred embodiment.

FIG. 5 is a block diagram of one module. The four XIN terminals mergeinto XIN which forms the input to XMIT PATH LOGIC 20, within which theswitching takes place to route the XMIT path to XOUTN, XOUTE, XOUTS orXOUTW. The four RIN terminals enter RECV PATH LOGIC 21 which selects oneRIN terminal for connection to ROUT which branches to the four ROUTterminals.

XIN is also connected to CON LOGIC 22 (configuration logic) whichdecodes commands and provides the above-mentioned selection signalsSELN, SELE etc and other commands, including READ and WRITE commands fora RAM UNIT 23. The command line CMND is fed to a clocked buffer 24 whichprovides complementary signals CMND (designating command mole) and CMNDBAR (designated "transmit mode"). Basically, in transmit mode the moduleacts simply as a link in the chain passing on both outward bound XMITpath data and inward bound RECV path data. In command mode the moduledetects whether a command token is present in its XMIT path logic and,if it is, decodes and obeys the command addressed thereto, i.e. timed toprovide a token bit in that module when CMND goes true.

CMND, CMND BAR and signals in general are gated with clock signals(described below) as is conventional in MOS circuits. For simplicitythis design detail is ignored in the present description.

The buffer 24 also detects a global reset signal (CMND true for just oneclock period) and generates an internal initialization signal INIT BAR(i.e. initialization asserted when the signal is false). This is readilydetected by logic which generates INIT BAR in response to the statesequence TMODE, CMODE, TMODE in successive clock periods. Theinitialization is global because INIT BAR is generated by every module,regardless of what is received at XIN along the XMIT path itself. Theuse of global reset is described below.

The function unit of the module is a 16k RAM UNIT 23. In the presence ofWRITE, 16k of data from the XMIT PATH LOGIC 20 is written into the RAMUNIT via a line RID (RAM input data). In the presence of READ, 16k ofdata is passed to the RECV PATH LOGIC 21 via a line ROD (RAM outputdata).

A timing pulse generator 25 provides multiphase timing pulses PHASECLOCKS in response to WCK. Although PHASE CLOCKS are shown connectedonly to CON LOGIC 22, they are of course distributed to the modulecircuits generally.

A module has seven mutually exclusive states asfollows:______________________________________SELN asserted (link tomodule above)SELE asserted (link to module to right)SELS asserted (linkto module below)SELW asserted (link to module to left)READ assertedWRITEassertedRESET (none of the aboveasserted).______________________________________

The CON LOGIC also provides a signal RPON (RAM power on) to switch onthe RAM power supply. RPON is reset by INIT BAR and can be toggled by acommand addressed to a module. Another command provides a strobe ACR(address counter reset) to the RAM UNIT 23 to reset its address counterat the instant of the strobe.

The RAM UNIT 23 is not essential to the operation of a module as a linkin a chain. It can be independently switched on and off by means ofRPON. Thus the chain of "good" modules can be grown having regard to theoperability of the control logic 20, 21, 22, 24, 25. If a module isencountered with bad control logic, the chain will have to be retractedand a new module in a different direction tried. This will be thesituation at the edge of the wafer; a non-existent module willinevitably appear to be bad. The control logic is permanently connectedto the power lines but is of small area and defects are unlikely toaffect wafer yield much. However the RAM UNIT, if faulty, could drawheavy current and collapse the voltage on the power tracks 11 and 12 towhich it is connected, so affecting large numbers of neighbouringmodules.

As shown in FIG. 6, the RAM UNIT 23 includes a switching transistor 30which is controlled by RPON via a charge pump 31 which turns thetransistor 30 on hard when RPON is true and connects V_(DD) to four 4kRAM blocks 32 and a free-running, 14 bit address counter 33 (2¹⁴ =16384)which can be reset by ACR for a purpose described below. The RAM datainputs are connected to the common input line MID (RAM input data) whichaccepts data from the XMIT PATH LOGIC. The RAM sense amplifiers 34 areconnected to the common output line ROD (RAM output data) which passesdata to the RECV PATH LOGIC.

The detailed management of the RAM's is effected conventionally by aclock generator 35 which receives the PHASE CLOCKS, READ and WRITE andeffects precharge, discharge, refresh and so on, in a manner which neednot be described here. However it should be noted that the counter 33comprises a 7-bit column counter (least significant half) and a 7-bitrow counter (most significant half). Every time a carry propagates fromthe column counter to the row counter, a signal REFR is given to theclock generator 35 and the currently addressed row is refreshed in wellknown manner. Thus refresh takes place every 128 (2⁷) clock pulses and acycle of 128×128 clock pulses is required to refresh all rows of the RAMblocks 32.

The purpose of ACR is to enable the address counters 33 in the variousmodules to stagger their refresh cycles so that only a few RAM UNITS 23are refreshing in any one clock period. This avoids excessive demands onthe power lines and introducing of noise spikes.

The address counter carry bit is denoted ACCO (address counter carryout) and this may also be utilized in one test facility to be describedbelow.

FIG. 7 is a detailed diagram of the XMIT PATH LOGIC 20. XIN is connectedthrough an FET 40 enabled by CMND BAR to a clocked 1-bit stage 41, fromwhich drive is provided to the XOUT lines. Each such line includes afirst FET 46 which is normally enabled by a validation latch 47 and asecond FET 48 of which only one is enabled by the corresponding signalSELN, SELE, SELS or SELW. The validation latch 47 provides a safetyfeature. As will be described below, when a command is addressed to amodule or INIT BAR is asserted, the CON LOGIC asserts a reset signalRESET BAR which resets any SEL signal which is set. Failure for this totake place is a recipe for disaster. If one SEL signal remainserroneously asserted when another is subsequently commanded, it ispossible to have the chain branching from one module in an uncontrolledmanner. This state of affairs is precluded by the validation latch 47which is enabled by RESET BAR and normally (with all of SELN to SELWfalse) latches the state which provides VALID and so enables all of theFET's 46. However, if any of SELN to SELW is true, the other state islatched to disable the FET's 46. This will prevent the module inquestion being used to add any other module to the chain, i.e. itbecomes a totally bad module and during the chain growth and test phase,the chain will be retracted and re-routed to avoid this module.

When the module is merely being used as a link in the chain and CMND BARis accordingly asserted, XIN is connected to one of XOUTN, XOUTE, XOUTS,XOUTW through FET 40, 1-bit stage 41, one of the FETs 46 and whicheverof the FETs 48 is enabled.

When the module is writing data to the RAM UNIT 23, CMND BAR is againasserted and the data passes through the FET 40 and 1-bit stage 41 toRID.

The output of the 1-bit stage 41 is fed back to the input of the stagethrough an FET 49 which is enabled by CMND to form a 1-bit latch whichlatches the bit therein at the time CMND is asserted. This output isXPLO (transmit path latch out), which is physically the same as RID.XPLO is what tells the CON LOGIC 22 whether the module in question isaddressed or not when CMND is asserted.

FIG. 8 shows the RECV PATH LOGIC 21. RINN, RINE, RINS and RINW areconnected through respective FET's 50 to a node 51. The FETs 50 areenabled by SELN, SELE, SELS and SELW respectively. The node 51 isconnected through an FET 52 enabled by HOLD and a clocked 1-bit stage 53to ROUT. The function of HOLD will be explained below but, forunderstanding of FIG. 8 it suffices to know that it is true consequenton CMND BAR is true, so that the module is established as a link in thechain, connecting the correct one of RINN to RINW to ROUT.

In order to transfer data from the RAM UNIT 23 to the RECV path, ROD isconnected to the input of the 1-bit stage 53 through an FET 55 enabledby READ. As one test facility a terminal TEST is connected to the inputof the 1-bit stage 53 through an FET 56 enabled by WRITE. TEST may beconnected to RID (FIG. 7) so that when a write operation is performed,the data sent to the module in question along the XMIT path is returnedfrom that module along the RECV path. The returned data can then bechecked against the transmitted data. This may be useful as part of dataverification procedures during normal use of the configured wafer.

Another use of TEST is implemented by connecting it to ACCO (FIG. 6).Then, during a write operation, a pulse should be injected into the RECVpath every 16k clock pulses. This may be useful to test the addresscounter 33 during the initial configuration procedures.

A further test facility, to be explained below is provided by a terminalSCAN OUT connected to the input to the 1-bit stage 53 through an FET 57which is enabled by a signal SHIFT which is complementary to HOLD.

The CON LOGIC 22 will now be described. FIG. 9 shows one part of thiscircuit which generates the above mentioned signals RESET BAR, HOLD andSHIFT and a signal TBIT which is a token bit to be shifted along a shiftregister described with reference to FIG. 10. XIN is connected through aFET 60 enabled by CMND BAR to a 1-bit stage 61. WRITE and READ are alsoconnected to the stage 61 which performs an OR function. The output ofthe 1-bit stage 61 is gated in a NAND gate 62 with CMND to provide RESETBAR which is also provided in response to INIT BAR by an AND gate 63.

The operation of this part of the circuit is as follows. If, in transmitmode, XIN provides a 1-bit it is buffered in the 1-bit stage 61. If CMNDis asserted before the next clock pulse, the output of the NAND gate 62goes false to force the output of the AND gate 63 false and thus assertRESET BAR. RESET BAR is asserted willy-nilly if INIT BAR is asserted,because this also forces the output of the AND gate 63 false.

The output of the 1-bit stage 61 is buffered for one more bit time by astage 64 to provide TBIT (token bit) which is a bit to be clocked downthe shift register (FIG. 10) so long as CMND is asserted. It should benoted that RESET BAR can only be asserted and TBIT generated when (1)the transmit path latch 41 contains a 1-bit when CMND is asserted or (2)READ or WRITE is asserted when CMND is raised, irrespective of thecontents of the transmit path latch. Case (1) represents the normal wayof addressing a command to a module: asserting CMND at the time a 1-bitis present in the module on the XMIT path. Case (2) provides a means ofaborting a WRITE or READ operation.

As explained above XPLO will be latched at 1 in an addressed chip. Asshown in FIG. 9, XPLO is applied to a 1-bit stage 67 through an FET 66enabled by CMND to provide SHIFT which enables the abovementioned shiftregister in order to clock TBIT along the register until CMND ceases tobe asserted, and complementary signal HOLD.

Detailed timing considerations are not entered into here but the generalsituation is that XPLO is one bit delayed relative to XIN and SHIFT is afurther bit delayed relative to XPLO. RESET BAR is one bit delayedrelative to CMND and TBIT is a further bit delayed. RESET BAR is thusgenerated off the same bit as is latched to form XPLO and one bit later,this same bit appears as TBIT to be clocked along the shift registerwith SHIFT true.

FIG. 10 shows the remainder of the CON LOGIC 22, consisting of a chainof eight clocked D-type flip-flops 70-77 forming the shift register anda T-type flip-flop 78. The passage of signals is controlled by gatessymbolically represented by small strokes with an adjacent S, meaningenabled by SHIFT or an adjacent H, meaning enabled by HOLD. Theflip-flops 70 to 75 provide SELN, SELE, SELS, SELW, READ and WRITErespectively. Assuming that the module in question is addressed it canbe seen that these six flip-flops will first be cleared by RESET BAR.Then TBIT will be clocked from flip-flop to flip-flop for as long asSHIFT remains true. When SHIFT becomes false and HOLD becomes true,which is when CMND goes false, the TBIT is latched in whichever flipflop it has reached.

If a 1-bit is sent down the XMIT path and CMND is asserted in the periodin which that bit enters a given module and is then held true for nclock periods, n=2 will cause TBIT to be latched in flip-flop 70 (SELN),n=3 will cause TBIT to be latched in flip-flop 71 (SELE) and so on.

If n=8, TBIT moves on to flip-flop 76 which provides ACR but does notstay latched because HOLD puts ground on the D input. Thus n=8 providesa means for resetting the address counter 33 of the RAM unit 23.

If n exceeds 9, TBIT then moves past the flip-flop 77 which providesSCAN OUT. SCAN OUT is injected into the RECV path as described withreference to FIG. 8 and can be detected at the RECV terminal. Theprovision of SCAN OUT is a demonstration that the CON LOGIC 22(excluding the flip-flop 78) is functioning. Accordingly it issatisfactory to use the module in the chain of modules, whether or notits RAM UNIT is functional.

If n=9, the flip-flop 78 is toggled. This flip-flop provides RPON and isreset by the global initialization signal INIT BAR, The preferred way ofconfiguring the system is to apply a global reset (CMND true for oneclock period, i.e. n=1) to ensure that all flip-flops, especially theRPON flip-flops of all modules are reset. The first module M1 (FIG. 4)is then tested with n greater than 9 and if SCAN OUT is detected back atRECV, all is well. If not another Ml must be selected and for thispurpose there are say four XMIT, RECV bondsites around the periphery ofthe wafer connected to different modules.

The first module M1 is then commanded with n=2 to latch SELN. In FIG. 4there is no wafer above M1 so when the notionally added M2 is testedwith n greater than 9, SCAN OUT will not appear. M1 is thereforecommanded with n=3 to latch SELE. M2 is tested with n greater than 9 andSCAN OUT appears. M2 is therefore commanded with n=2 to add M3 which istested with n greater than 9, and so on. The module address table isbuilt up to record for each module what its selection direction is.

When the maximum usage of the modules has been effected in this way, theRAM UNITS 23 are powered and tested one by one, e.g. sequentially fromM1 onwards. M1 is therefore commanded with n=9 to toggle the flip-flop78 on and assert RPON. The module is then commanded with n=8 to resetthe address counter 33 by ACR at the desired time relative to the datumaddress cycle time. The command resets SELE so the chain connected toXMIT again consists of M1 only although the more remote part of thechain remains in tact. WRITE and READ are now employed using commandswith n=7 and 6 respectively to see whether it is possible to write tothe RAM UNIT 23 and reliably read back what was written.

If the module fails this test, it is commanded again with n=9 to togglethe flip-flop 78 again and set RPON false. Whether RPON is left true orset false, M1 is again commanded with n=3 to latch SELE and re-join thechain. M2 is now tested by using commands with n=9 (toggle RPON on), n=7(WRITE) and n=6 (READ). RPON is toggled off if necessary and M2 iscommanded with n=2 to latch SELN, whereafter the testing proceeds to, M3and so on.

During this phase the aforementioned table is set up with its OFFSET andFLAG entries.

FIG. 11 shows the control circuitry for controlling the addressing ofthe modules. This circuitry may be off the wafer and interfaces with acontrol processor (not shown) which provides the necessary data and astrobe signal ENABLE which initiates a command operation. This processorstores the aforementioned table to enable it to time ENABLE and SERIALDATA correctly.

When ENABLE goes true (see also FIG. 12) it generates a 1 bit TOKEN viaflip-flops D1 and D2, whose outputs QD1 and QD2 BAR are shown in FIG.12, and an AND gate A1. The TOKEN is applied to XMIT via a multiplexer80. ENABLE also enables (EN terminal) a 9-bit displacement counter A2which is used to count the number of clock pulses to the module to beaddressed. A 9-bit counter will handle a chain of up to 512 modules. Thecounter 81 will have been preset by the control processor with thecorrect initial value denoted DISPLACEMENT DATA and, when enabled,counts clock pulses WCK until a terminal count BD is reached. BD islatched in a latch L1 whose output QL1 enables a second counter 82 andalso initiates CMND via an AND gate A2. The counter 82 is a 4-bitcommand counter present in accordance with the desired duration of CMNDby CMND DATA. When this counter reaches its terminal count BC a secondlatch L2 latches BC and the QL2 BAR output of this latch disables thegate A2, so terminating CMND. A 4-bit counter 82 suffices to set up alldesired durations of CMND from n=1 clock period (global reset) up ton=10 clock periods as required by the CON LOGIC 22 of FIG. 10.

Although not illustrated, QL2 BAR may be used to reset the. latches D1,D2, L1, L2.

When a WRITE command is set up, the controlling processor must feed theserial data to XMIT after CMND has gone low again and in doing this itapplies a signal WRITE SEL to the multiplexer 80 to connect SERIAL WRITEDATA to XMIT". When a READ command is set up, the controlling processormust be ready to accept serial read data from RECV m clock pulses afterthe termination of CMND, where m corresponds to the displacement of theaddressed module from RECV.

For simplicity and in order to avoid a greater risk of anomolousconditions it is preferred to assert CMND when there is only a singleTOKEN bit on the XMIT path. If more than one bit is on the path,multiple addressing will occur, with the same command given to alladdressed modules, because this is determined by the duration of CMND. Asingle TOKEN bit can be used to address a plurality of modules insequence. The bit is latched in the latch 41, 42 (FIG. 7) and, when acommand is terminated at one module, can continue to another module,which is addressed when CMND is asserted, provided the one module is ina state with one of its SEL signals asserted.

There are three reset modes for a module. As explained above, raisingCMND for one clock period only asserts INIT BAR in all modules, clearingthe shift register stages 70-77 (FIG. 10) in all modules and alsolowering RPON in all modules. Secondly, there is an addressed reset inthat RESET BAR is asserted in just the addressed module to clear theshift register stages 70 to 77 before the token TBIT is shifted in.Thirdly, these shift register stages are cleared if CMND is raised whilethe module is set to READ or WRITE, by virtue of the connections toamplifier 61 in FIG. 9. This is termed "operation reset" and may be usedin various ways called termination with onward addressing (TOA),termination with path closure (TPC) and ABORT.

TERMINATION WITH ONWARD ADDRESSING (TOA). In the case of the WRITEoperation, a `1` is appended to the end of the write data stream sothat, when CMND is raised AT THE END of the write operation, the moduleperforming the write sees a `1` in its XMIT path latch. The module istherefore once again an addressed module; raising CMND resets the shiftregister 70-72, so terminating the write operation and a new onward pathfrom the module may then be selected, by keeping CMND high for theappropriate number of clock pulses. In the case of the READ operation, asimilar scheme pertains, save that in this case the command token mustbe injected into the XMIT path at such a time that it arrives at thetarget chip when or after the last bit of data is being read out on tothe RECV path.

TERMINATION WITH PATH CLOSURE (TPC). In this case the XMIT path latch ofthe target module contains a `O` when the CMND line is raised at the endof the READ or WRITE operation. Raising the CMND line resets theshift-register, terminating the current operation. Unlike TOA, there isno command token present to generate an onward path. TPC will be usedwith a command token set at some module nearer XMIT so that, when CMNDis raised, a new path will be configured from THAT chip, or a read orwrite operation will be set up there.

ABORT. If CMND is raised at any time prior to the end of a complete reador write operation, that operation will immediately be terminated. Agraceful ABORT from a READ operation may be made by ensuring that theXMIT path is flushed with `0`s prior to the abort. A TOA- or TPC-likeABORT prior to the end of a READ operation is possible by injecting asingle `1` into the flushed XMIT path. It is more difficult to abort aWRITE operation gracefully as multiple module addressing will generallyoccur due to the presence of multiple `1`s in the XMIT path write datastream when CMND is raised. A possible solution is to keep CMND high forlong enough to ensure that all tokens passing through the shift register70-77 are scanned out on to the RECV path. The outputs of the shiftregisters 70-77 are therefore effectively when the CMND line iseventually lowered. It should be realised, however, that in this caseall chip-to-chip connections are broken and will have to bereestablished at some later time. Note that GLOBAL RESET should NOT beused in place of an ABORT, as a global reset will cause all RAM powersupplies to be switched off, thereby losing all the data on the wafer.

I claim:
 1. A system of circuit modules connected in a chain, eachmodule having an input terminal and an output terminal connected to saidinput terminal of the next module in the chain, each module including afunction unit for operating on data and control means for causing themodule to execute selected ones of a repertoire of commands, saidcontrol means of each module including serial logic connected from saidinput terminal to said output terminal of said module, for passingdigital signals from module to module, said control means of each modulecomprising a shift register arrangement comprising a series of shiftregister stages, at least one of which is included within said seriallogic and said system comprising a source of clock pulses distributed toall said shift register arrangements for clocking digital signalstherethrough, a power supply source connected to all modules, means forlaunching a token consisting of at least one bit into said chain to beclocked by said clock pulses along said serial logic of said modules insequence, a global command line extended to said control means of allsaid modules for the application of global command signals substantiallysimultaneously to all said control means, and means for applying a firstcommand signal to said global command line at a predetermined time aftersaid token was launched and, when said token is present in said seriallogic of a selected module, said control means being responsive toreceipt of said first command signal coincidentally with the presence ofsaid token to execute a first selected one of said repertoire ofcommands.
 2. A system according to claim 1, wherein said shift registerarrangement of each module further comprises at least one stagebranching off said serial logic to form a branch portion of said shiftregister arrangement, and wherein said first selected command executedin said selected module causes said token to be diverted from saidserial logic into said branch portion to be clocked therealong by saidclock pulses.
 3. A system according to claim 2, wherein said seriallogic of each module carries both tokens and data sent to the modules.4. A system according to claim 2, wherein said serial logic of eachmodule provides a single bit delay per module through said chain.
 5. Asystem according to claim 2 wherein said control means of each module isresponsive to a second command signal applied to a global command lineto execute one of said repertoire of commands determined by the positionof said token in said branch portion logic at the time of occurence ofsaid second command signal.
 6. A system according to claim 5, whereinboth said first and second commands are applied to the one said globalcommand line.
 7. A system according to claim 6, wherein said first andsecond command signals are given by the assertion and terminationrespectively of a predetermined signal level on said global commandline.
 8. A system according to claim 7, wherein each said shift registerarrangement includes a stage for toggling a power supply control signalwhich determines whether or not power is supplied from said power supplysource to circuits of said function unit and wherein each module furthercomprises circuit logic responsive to assertion of said predeterminedsignal level on said global command line for a predetermined minimumduration to reset said power supply control signal, whereby suchassertion removes the power supply from function unit circuits of allmodules.
 9. A system according to claim 5, wherein said token is asingle token bit and said control means are responsive to said token bitlatched in a particular stage of said shift register arrangement onreceipt of said second command signal to determine which of saidrepertoire of commands is executed.
 10. A system according to claim 9,wherein said control means is operative to reset at least some stages ofsaid shift register arrangement before said token is clocked along saidshift register arrangement.
 11. A system according to claim 10, whereinsaid control means of each module includes configuration logic wherebythat logic can select one of a plurality of neighboring modules as thenext module in said chain, and wherein said repertoire of commandsincludes commands to the configuration logic for effecting theselection, and further comprising means adapted to disable saidconfiguration logic if any one of the neighbouring modules remainsselected after said reset.
 12. A system according to claim 1, whereineach said shift register arrangement includes a stage for toggling apower supply control signal which determines whether or not power issupplied from aid power supply source to circuits of said function unit.13. A system according to claim 1, wherein said function unit is amemory unit, said chain includes an outbound path comprising said seriallogic and along which tokens and data may be sent and an inbound pathalong which data may be returned, and wherein the repertoire of commandsincludes a write command to which said control means is responsive toconnect said inbound path to said memory unit for writing data into saidmemory unit, and a read command to which said control means isresponsive to connect said outbound path to said memory unit for readingdata from said memory unit.
 14. A system according to claim 13, whereinsaid memory unit of each module includes a free running address counterfor addressing locations into which the data is written or from whichthe data is read.
 15. A system according to claim 14, wherein said shiftregister arrangement includes a stage for providing a reset signal tosaid address counter.
 16. A system according to claim 1, wherein saidcontrol means of each module includes configuration logic whereby thatmodule can select one of a plurality of neighbouring modules as the nextmodule in said chain, and wherein said repertoire of commands includescommands to the configuration logic for effecting the selection.
 17. Asystem according to claim 1, wherein the modules are an array ofintegrated circuits on a wafer.
 18. A wafer-scale integrated circuitmemory system including a plurality of circuit modules on a wafer, eachmodule including a random access memory unit addressed by a free-runningcounter and having a data output and a data input, an outbound data pathhaving an input and an output whereby data maybe sent through the moduleto another module, an inbound data path having an input and an outputwhereby data maybe sent back through the module from another module,configuration logic for selecting which of a set of neighbouring modulesis connected to said outbound data path to receive data sent on theoutbound data path and is connected to said inbound data path input toact as the source of data sent back on the inbound data path, said inputof said outbound data path being connected to the outputs of theoutbound data paths of said set of neighbouring modules and said outputof said inbound data path being connected to the inputs of the inbounddata paths of said set of neighbouring modules, and control meansoperable to select between a plurality of mutually exclusive states,namely, a set of first states in one-to-one correspondence with the saidneighboring modules for causing said configuration logic to select aneighbouring module, a read state in which a connection is enabledbetween said data output of said memory unit and said inbound data pathto pass read data to said inbound data path output from the addresses ofsaid random access memory unit addressed by said free-running counterduring the continuance of said read state and a write state in which aconnection is enabled between said data input of said memory unit andsaid outbound data path to receive write data from said outbound datapath input for writing into the addresses of said random access memoryunit addressed by said free-running counter during the continuance ofsaid write state, wherein said control means comprise a shift registerhaving a plurality of stages corresponding to said states respectively,and the presence of a bit in one of said stages selects a correspondingone of the said stages, said system further comprising means forlaunching a token bit at said outbound data path input of a first one ofsaid modules, a global command line connected to all modules and meansfor applying a command signal to said global command line apredetermined time after said token bit is launched, and wherein eachsaid control means is responsive to said command signal to clock saidtoken bit down said shift register of that module in which said tokenbit is present on said outbound line thereof when said command signalgoes from a datum level to an active level and to cease clocking saidtoken bit down said shift register when said command signal resets tosaid datum level.
 19. An array of circuit modules connectable in achain, each module having a set of input terminals and a set of outputterminals each said output terminal being connected to one of said inputterminals of an adjacent module in said array, each module including afunction unit for at least storing data, switching means for selectingone of said output terminals and control means for causing the module toexecute selected ones of a repertoire of commands, said control meanscomprising first logic means through which said input terminals areconnected to said switching means and second logic means including ashift register, said system further comprising a source of clock pulsesdistributed to said shift registers of all said modules for clockingdigital signals therethrough, a power supply source connected to allmodules, means for launching a token consisting of at least one bit intoone of said module inputs to be clocked by said clock pulses throughsaid first logic means to said switching means of said modules insequence, a global command line extended to said control means of allsaid modules for the application of global command signals substantiallysimultaneously to all said control means, and means for asserting acommand signal on said global command line at a predetermined time aftersaid token was launched and for terminating the assertion of saidcommand signal after a predetermined delay, said first logic means beingresponsive to assertion of said command signal when said token ispresent in said first logic means to start a command bit clockingthrough said stages of said shift register, until said command signalceases to be asserted after said predetermined delay, said stages ofsaid shift register corresponding to said commands respectively of saidrepertoire and said control means comprising means operative when saidcommand signal ceases to be asserted to implement said commandcorresponding to that one of said shift register stages in which saidcommand bit has stopped.
 20. An array of circuit modules according toclaim 19, wherein said commands include commands in one to onecorrespondence with said output terminals, each said command operatingsaid switching means to select said corresponding output terminal.
 21. Asystem of circuit modules connected in a chain, each module having aninput terminal and an output terminal connected to said input terminalof the next module in the chain, each module including a function unitfor at least storing data and control means for causing the module toexecute selected ones of a repertoire of commands, said control means ofeach module comprising a shift register arrangement having a series ofshift register stages and said system comprising a source of clockpulses distributed to all said shift register arrangements for clockingdigital signals therethrough, a power supply source connected to allmodules, means for launching a token consisting of at least one bit intosaid chain to be passed from said input terminal to said output terminalof said modules in sequence, a global command line extended to saidcontrol means of all said modules for the application of global commandsignals substantially simultaneously to all said control means, andmeans for applying a command signal to said global command line at apredetermined time after said token was launched and, when said token ispassing through a selected module, said control means being responsiveto receipt of said command signal coincidentally with the presence ofsaid token to start clocking a command bit through said shift registerstages, to arrest said command bit when said command signal terminatesand to execute a selected one of said repertoire of commands independence upon which of said shift register stages said command bit hasbeen arrested in.